1. Field of the Invention
The present invention relates generally to a memory card including a flash memory module. More particularly, the invention relates to a memory card incorporating a hardware accelerator to improve the performance of read operations performed by the memory card.
2. Description of Related Art
Memory cards are commonly used to store and access information in digital devices such as personal digital assistants (PDAs), portable audio devices, cellular phones, and personal computers. A typical memory card comprises a non-volatile memory and a corresponding memory controller providing an interface between the memory card and a host system.
Various memory cards are disclosed, for example, in U.S. Patent Publications Nos. 2004-0205301 and 2004-0236909, and U.S. Pat. No. 6,131,139.
FIG. 1 is a block diagram showing a general layout of a memory card 100 connected to a host system 200. Referring to FIG. 1, memory card 100 comprises a flash memory module 120 and a memory controller 140. Host system 200 communicates with flash memory module 120 through memory controller 140. In particular, host system 200 may perform read, program, and erase operations on flash memory module 120 through memory controller 140.
Memory cells in flash memory module 120 are organized into blocks and pages. Each block generally comprises one or more pages and each page generally comprises a plurality of memory cells for storing a specified number of bytes. For example, a one (1) gigabyte (GB) NAND flash memory module may be organized into 8192 blocks, where each block comprises 32 pages, and each page stores 512 bytes of data.
In flash memory module 120, data is read or programmed a page at a time, and erased a block at a time. Accordingly, whenever host system 200 performs a read or program operation on flash memory module 120, a page of data is transferred to or from flash memory module 120.
The performance of read, program, and erase operations in flash memory module 120 can be improved by increasing the size of each block. In addition, increasing the block size can also reduce the chip size of flash memory module 120 by reducing the amount of peripheral circuitry per byte required to control each block. The block size is generally increased by increasing either the number of pages in each block, or the number of bytes in each page.
FIG. 2 shows two blocks with different block sizes: a “small block” and a “large block”. The small block comprises 32 pages, each having a page size of 512 bytes (B). The pages are arranged in 32 rows, with each row representing a single page. The large block, on the other hand, comprises 64 pages, each having a page size of 2 kilobytes (KB). The pages in the large block are arranged in 64 rows, where each row stores a single 2 KB page. However, to simplify FIG. 2, not all 64 pages are shown.
Within the large block, each 2 KB page can be divided into four (4) “small pages” of 512 bytes each. The small pages in the large block can be accessed by specifying a row and a start column (indicated by arrows) in the large block. In this written description, the term “small page” is used to indicate a section of a large block having the same size as a page in a small block.
The respective sizes of the small and large blocks in FIG. 2 are used merely as examples. In practice, the number and sizes of pages in the small and large blocks can vary. However, a small block generally has at least one dimension that is smaller than a corresponding dimension in a large block, and page addresses in small blocks can be mapped onto page addresses in large blocks. In this written description, addresses in small blocks are referred to as “small block addresses”, and addresses in large blocks are referred to as “large block addresses”.
Both small block addresses and large block addresses include a memory block address and a page address. The memory block address indicates a block in flash memory module 120 where the address is located, and the page address indicates a page in flash memory 120 where the address is located.
To illustrate a logical mapping between a small block and a large block, the pages in the small block are labeled 0P through 31P. A large arrow is included in FIG. 2 to show the correspondence between logical addresses in the small block and physical addresses in the large block. Such a logical mapping may be required, for example, where host system 200 is designed to access data using small block addresses, yet the flash memory module 120 is accessed using large block addresses. In other words, if host system 200 sends memory controller 140 a small block address, memory controller 140 must convert the small block address into a large block address in order to access flash memory module 120.
For instance, suppose host system 200 sends a read command to memory controller 140 with an address for a page 1P in the small block. Memory controller 140 must convert the address for page 1P into a physical address in the large block. As shown in FIG. 2, page 1P is located at row 1, column 0 of the small block, and row 0, column 1 of the large block.
Unfortunately, the address conversion requirement slows down read operations in flash memory module 120, thereby degrading the overall performance of the memory card.